The following is a description of the design evolution of transmit (TX) driver circuits for rates up to 15 Gbps on a 32 nm process.
In a number of applications the classical current mode logic (CML) stage with a resistive load has been used as a driver of a transmission line with a 100Ω differential characteristic impedance. However, this type of circuit was found to have a limitation related to maintaining constant output impedance not dependent on an output state driven by the data-stream. This appears in low headroom by supply conditions when targeting the specified output swing of 1 Vppd.
The reduction of gate oxide thickness dictates reduction of supply voltage for CMOS logic circuits. The goal for the analog circuitry is to operate in the same supply domain of 1.0V as the 32 nm CMOS logic operates. This is possible with the right choice of circuit topologies in the analog design.
Ignoring the above non-linear issues, or assuming—solved, achieving a wide band of impedance matching is known to be possible by compensating the parasitic capacitances with use of inductors in shunt, series, series-shunt or “T-coil” configuration. All of these techniques work by splitting the contributors of total output capacitance.
These techniques should be applicable with any choice of driver stage.
Still, the limitations for applying these techniques are:
If the contributors of capacitance which could be split by an inductor have largely incomparable capacitance and the largest one cannot be split, or
If after splitting the capacitances the connectivity of one of them is being switched in circuit operation between nets with different potentials.
The linearity of the termination over the dynamic range of the output swing is limited by the shunting impedance of the transistors, driving the output port.
In the classical CML type driver stage 100 the amplitude is defined simply by a DC control on a tail current by transistor M3. The steering pair of transistors M1 and M2 operates in large signal mode, switching the common mode current to one of the half-output terminals defining two settled output states. If transistors M1 and M2 do not remain in saturation over the full output swing, the capacitance of the common source net CTAIL would be connected through a transistor in linear mode to one of the half-output ports, and thus it would cause data-dependent modulation of the reflection coefficient of the differential port.
It should be noted that for natural reasons CTAIL>>C0. This is so because the two source terminals of the steering transistors plus the drain terminal of the current source have at least three times higher total capacitance than the one of the drain terminal of one steering transistor. This is the bottom limit of the capacitive ratio CTAIL/C0, which comes from pure theoretical geometrical considerations.
The asymmetry between the impedance of one half-output to the complementary one half-output (in the frequency band below the zero, introduced by resistance of the transistor in linear mode), is:
                    Z        high                    Z        low              =                            R          LOAD                ||                  C          0                                      R          LOAD                ||                  (                                    C              0                        +                          C              TAIL                                )                                        C        TAIL            ≥              3        ×                  C          0                      =                  >                                  ⁢                              Z            high                                Z            low                              =                                    R            LOAD                    ||                      C            0                                                R            LOAD                    ||                      4            ⁢                                                  ⁢                          C              0                                          
The at least four times larger reactive load on the half-output versus the complementary one makes a mismatch in a limited band with the line impedance.
By TDR measurements it has been found that the half side impedances asymmetry is 50:37Ω. Besides causing reflection and reducing insertion to the differential line, it also causes asymmetry and thus, for common mode to differential conversion and vice versa, what leaks X-talk through supply rails direct coupling between TX/TX and between TX/RX channels (Far End Cross-Talk (FEXT) and Near End Cross-Talk (NEXT)—respectively).
The capacitance C0 practically could be compensated by an on-chip inductor relatively simply. However, the capacitance CTAIL is first—a large value and second—its connectivity to the output being switched in the operation of the circuit.
What is desired is a simple driver circuit that overcomes the limitations of the prior art discussed above.